PAPILIO ONE 500K
The Papilio One 500K comes fully assembled with a Xilinx XC3S500E and 4Mbit SPI Flash memory.
Papilio is an open-source FPGA project intended for education, hobbyists, engineers, or anyone interested in learning Digital Electronics in a friendly community.
Papilio One Specifications
- Four independent power rails at 5V, 3.3V, 2.5V, and 1.2V.
- Power supplied by a power connector or USB.
- Two channel USB connection for JTAG and serial communications implemented with FT2232.
- EEPROM memory to store configuration settings for FT2232 USB chip.
- Spartan 3E FPGA
- 32MHz oscillator that can be used by Xilinx's DCM to generate any required clock speed.
- VTQFP-100 footprint that supports Xilinx XC3S100E, XC3S250E, and XC3S500E parts.
- Bank 0-3 can be jumpered to support 1.2V, 2.5V, or 3.3V.
- Xilinx JTAG header supports Xilinx JTAG cables.
- Power and I/O are routed to the side headers.
- Board can be used with Bread Boards if only the outside row of the side headers is populated.
- Easily add new functionality to the Papilio One with Wings that snap onto the board.
- 48 bidirectional I/O lines which can be split up as:
1 - 32 Bit Wing or
3 - 16 Bit Wings or
6 - 8 Bit Wings
For more information including quickstart guides and all downloads visit the Papilio.cc community.
This open source hardware and software is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. If you can't accept this risk, please do not buy this hardware.